1. Field of the Invention
The present invention relates to peripheral devices in computer systems, and more particularly to a system with a centralized core logic register for maintaining status information for peripheral devices in a computer system.
2. Related Art
Computer systems typically include a central processing unit that is coupled to and communicates with a plurality of peripheral devices, typically through a computer system bus. These peripheral devices can include: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller. A peripheral device frequently requires attention from the central processing unit in order to transfer data between the central processing unit and the peripheral device, or to otherwise command and manipulate the peripheral device. This attention is typically triggered by an interrupt, which the peripheral device sends to the central processing unit on order to "interrupt" normal processing by the central processing unit. During an interrupt, the central processing unit temporarily suspends normal processing and executes a piece of code known as an "interrupt service routine" to perform the required service for the peripheral device. Once the interrupt service routine is complete, the central processing unit resumes normal processing.
Many computer systems use a shared interrupt architecture, in which a plurality of peripheral devices can activate the same interrupt signal. One commonly-used shared interrupt architecture is a daisy-chained structure, in which peripheral devices are "chained" together through one or more interrupt lines. Any peripheral device in the chain can generate an interrupt signal, and this interrupt signal is passed through the chain until it ultimately reaches the central processing unit. In another commonly-used shared interrupt architecture, peripheral devices share a common interrupt bus line; peripheral devices can signal an interrupt to the processor by asserting this interrupt bus line.
A shared interrupt architecture has certain advantages. It is very simple; typically requiring only a small number of signal lines to carry interrupt signals. It is also expandable, typically allowing additional peripheral devices to be integrated into a computer system without requiring additional lines for interrupt signals.
However, a shared interrupt architecture suffers from a major disadvantage. It requires the central processing unit to determine which peripheral device requires processing. This is because all of the peripheral devices generate the same interrupt signal, and the central processing unit cannot tell from the interrupt signal which peripheral devices require servicing. Hence, the central processing unit must typically "poll" the peripheral devices in order to determine which peripheral devices require servicing.
This polling process can be quite time-consuming. The central processing unit may have to poll every peripheral device in the computer system, even though only one peripheral device typically requires servicing at any given time. Polling reduces CPU efficiency, because the CPU must perform multiple bus transactions to poll the peripheral devices, and each bus transaction can require a large number of CPU cycles in a high performance computing system. Polling also ties up the peripheral bus with a large number of polling accesses. Furthermore, polling increases the time required for servicing an interrupt. This may create problems for peripheral devices that require servicing in a timely manner. For example, a network interface controller may require immediate servicing to prevent a buffer of incoming data from overflowing. This immediate servicing may be delayed by polling.
What is needed is a system for retrieving status information from peripheral devices in a shared interrupt architecture that reduces the amount of time and bus activity required to determine the status of the peripheral devices.